1. Field
Embodiments relate to acquiring images with pixel arrays. In particular, embodiments relate to acquiring images with complementary metal oxide semiconductor (CMOS) pixel arrays.
2. Background Information
FIG. 1 is a block diagram of a known image sensor package 100 that includes an image sensor 101 having a complementary metal oxide semiconductor (CMOS) pixel array 102, control circuitry 103, and readout circuitry 104. Commonly, the CMOS pixel array, the readout circuitry, and the control circuitry are monolithically integrated on a single die or other substrate. The image sensor package provides interconnections (not shown), such as pads, to connect the image sensor with an external signaling medium (e.g., circuitry of a digital camera or other system having the image sensor package).
The CMOS pixel array 102 includes a two-dimensional array of CMOS pixels (e.g., pixels P1, P2, . . . Pn). As illustrated, the pixels are arranged in rows (e.g., rows R1 through Ry) and columns (e.g., column C1 through Cx). Commonly there may be anywhere from hundreds to many thousands each of rows and columns of pixels. During image acquisition, the pixels may acquire image data (e.g., photogenerated electrical charges). The image data from all of the pixels may be used to construct an image as is known in the art.
The control circuitry 103 and the readout circuitry 104 are coupled with the CMOS pixel array. The control circuitry is operable to apply electrical signals to the CMOS pixel array to control or assist with controlling aspects of image acquisition. The readout circuitry is operable to read out the image data from the pixels. Commonly, the readout circuitry may read out image data from a single row of pixels at a time along column readout lines 105. The column readout lines are also sometimes referred to as bitlines. The readout circuitry may potentially include amplification circuitry, analog-to-digital conversion (ADC) circuitry, gain control circuitry, or the like. The image data signals 106 may be provided from the readout circuitry to an external signaling medium (e.g., circuitry of a digital camera or other systems having the image sensor package).
The CMOS pixel array 102 commonly uses an electrical rolling shutter. During the image acquisition process, the CMOS pixel array may be exposed to constant and/or continuous light 107 and the electrical rolling shutter may control the amount of exposure that the pixels of the CMOS pixel array are subjected to under the constant/continuous light. For example, in an electrical rolling shutter each row of pixels may be exposed to light during a different period of time in a rolling or sequential fashion. For example, for each acquired image the rows of pixels may be exposed to light sequentially row-by-row from the first row R1 to the last row Ry. As shown, clock signals 108 and rolling shutter image acquisition control signals 109 may be provided to the control circuitry from an external signaling medium (e.g., circuitry of a digital camera or other systems having the image sensor package). The control circuitry may apply electrical signals to the CMOS pixel array based on the received clock and control signals to implement the electrical rolling shutter operations.
FIG. 2 is a circuit diagram illustrating known pixel circuitry 202 for two four-transistor (4T) pixels P1 and P2 of a CMOS pixel array. The pixels P1 and P2 are arranged in two rows and one column and time share a column readout line 205. By way of example, the pixel circuitry may be implemented in the pixels P1 and P2 of the CMOS pixel array 102 of FIG. 1.
Each of the pixels includes a photodiode PD, a transfer transistor T1, a reset transistor T2, an amplifier or source-follower SF transistor T3, a row select transistor T4, and a floating diffusion node FD. Within each pixel, the photodiode is coupled to the floating diffusion node FD by the intervening transfer transistor T1. A transfer signal TX asserted on the gate of the transfer transistor T1 activates the transfer transistor T1. The floating diffusion node FD may represent a circuit node to receive and hold a charge. The reset transistor T2 is coupled between a supply voltage VDD and the floating diffusion node FD. A reset signal RST asserted on the gate of the reset transistor T2 activates the reset transistor T2. The source-follower SF transistor T3 is coupled between a voltage supply VDD and the row select transistor T4. The source-follower SF transistor T3 has a gate coupled to the floating diffusion node FD and a channel selectively coupled to the column readout line 205 through the row select transistor T4. The source-follower SF transistor T3 is coupled to the column readout line when a row select signal SEL is asserted on the gate of the row select transistor T4. The row select transistor T4 selectively couples the output of the pixel to the column readout line 205 when the row select signal SEL is applied to the gate of the row select transistor T4.
FIG. 3 is a plot illustrating timing of known electrical rolling shutter image acquisition control signals that are suitable for implementing an electrical rolling shutter for two rows of a pixel array. Electrical rolling shutter image acquisition control signals are plotted for each of two rows, namely row R1 and row R2, on the vertical axis. Progression of time is plotted from left to right on the horizontal axis. To facilitate description, the electrical rolling shutter image acquisition control signals are described in conjunction with the components and signals of the pixels P1 and P2 of FIG. 2.
Referring to the electrical rolling shutter image acquisition control signals for row R1, the gate of the reset transistor T2 is initially activated by application of a reset signal RST at time t1. While the gate of the reset transistor T2 is activated, a gate of the transfer transistor T1 is pulsed with a transfer signal TX between times t2 and t3. As a result, the photodiode PD and the floating diffusion node FD are reset to the supply voltage VDD. The transfer signal TX is de-asserted at time t3. After the reset, the production and accumulation of photo-generated charges in the photodiode PD begins. The production and accumulation of photo-generated charges in the photodiode PD is also referred to herein as integration. As previously mentioned, there is typically constant/continuous light to expose the photodiode PD throughout the integration. The photodiode PD is operable to generate charges (e.g., photogenerated electrons or holes) in response to such light. As photogenerated charges, for example electrons accumulate on the photodiode PD, its voltage may decrease, since electrons are negative charge carriers (or in the case of photogenerated charges being holes, the voltage may increase accordingly). The amount of voltage or charges accumulated on the photodiode PD may be indicative of the amount and/or intensity of the light incident on the photodiode PD during the exposure period, and may represent image data. For constant intensity light, the longer the exposure period, which is determined by the particular electrical rolling shutter, the more the accumulation of charges.
The reset signal RST may be de-asserted at time t4 to electrically isolate the floating diffusion node FD. A select signal SEL is asserted to the gate of the row select transistor T4 at time t5. This prepares the row R1 of pixels for readout. The gate of the transfer transistor T1 is activated by application of the transfer signal TX between times t6 and t7. This causes the transfer transistor T1 to transfer the photo-generated charges (e.g., electrons) accumulated in the photodiode PD to the floating diffusion node FD. The charge transfer may cause the voltage of the floating diffusion node FD to drop from the supply voltage VDD to a second voltage that is indicative of the image data (e.g., photogenerated electrons accumulated on the photodiode PD during the exposure period). Integration ends upon the finish of the charge transfer. The floating diffusion node FD is coupled to control the gate of the source-follower SF transistor T3. The floating diffusion node FD is presented to the gate of the source follower SF transistor T3. Source-follower SF transistor T3 operates to provide a high impedance connection to the floating diffusion node FD. The source follower SF transistor T3 amplifies the photogenerated charge signal, which is read out to column readout line 205 by row select transistor T4. The row select signal SEL applied to the row select transistor T4 is deactivated at time t8. This completes the readout operation.
As shown, in an electrical rolling shutter, the signals for row R2 each start a predetermined time after the corresponding signals for row R1. That is, each control signal (i.e., RST, TX and SEL) for row R2 is asserted after its counterpart control signal for row R1 has been asserted. The first row R1 is reset, integration is initiated, and then the first row R1 is readout generally a predetermined time after reset. Similarly, the second row R2 may be reset a predetermined time after resetting the first row R1, integration in the second row R2 may be initiated, and then the second row R2 may be readout after the first row R1 has been readout. Notice that integration for row R2 occurs after integration for row R1. It is common that the integration for row R2 starts during the time that the integration for row R1 is taking place. It is noted that the signals in the illustration are not drawn precisely to scale. Such a process may be repeated for all of the other rows of pixels of a CMOS pixel array, sequentially, row-by-row, from the first row R1 to the last row Ry, for each acquired image.
FIG. 4 is a block diagram of a known reset-readout block 410 that represents the reset and readout operations performed when acquiring a single image frame using an electrical rolling shutter. Progression of time 411 is plotted on the vertical axis from top to bottom. The reset-readout block has the shape of a parallelogram. A left vertical side of the parallelogram represents a reset line 412. The reset line is bounded between resetting of the first row R1 (at the top left corner of the parallelogram) through the resetting of the last row Ry (at the bottom left corner of the parallelogram). The intermediate rows between R1 and Ry are reset sequentially row-by-row or one-by-one after the first row R1 though the last row Ry. A right vertical side of the parallelogram represents a readout line 413. The readout line is bounded between readout of the first row R1 (at the top right corner of the parallelogram) through readout of the last row Ry (at the bottom right corner of the parallelogram). The intermediate rows between R1 and Ry are readout sequentially row-by-row or one-by-one after the first row R1 though the last row Ry. The resetting of rows R1 to Ry typically takes the same amount of time as the readout of rows R1 to Ry.
Within an image frame, each row is initially reset and then subsequently read out after a generally predetermined time. The time between the resetting of the row, and readout of that row, represents the exposure period during which the pixels of that row are configured to perform photoelectric charge production and accumulation (i.e., integration). As illustrated by arrow 407, there is typically constant/continuous illumination from at least the resetting of the first row R1 through the readout of the last row Ry. Notice also that the readout of the first row R1 typically begins well before the resetting of the last row Ry. This is typically done to help reduce the overall amount of time needed to acquire an image frame.